Contribution à l'étude expérimentale des résistances d'accès dans les transistors de dimensions deca-nanométrique des technologies CMOS FD-SOI

Abstract : The reduction of the dimensions of field effect MOS transistors has slowed down during the last years due to the increasing importance of parasitic factors such as access resistance. As a matter of fact, channel miniaturisation was accompanied by a reduction of its intrinsic resistance while that of the access region at the frontier with the channnel stayed constant or increased. The goal of this thesis was to set a new electrical characterization method to take into account this parasitic component long considered negligible in by industrials.In the first chapter, CMOS technologies working and its FD-SOI adaptation specificities are presented. The second half of the chapter deals with the state of the art of electrical characterization and their hypothesis about access resistance.The second chapter present a new resistive and capacitive parasitic components extraction method using transistors of close channel length. The results are then compared to existing models from which, a new one more physically accurate is proposed.The third chapter expose a new electrical characterization method based on Y function allowing the analyze of transistor behavior on the whole working regime. This new method is then combined with the one developped in the previous chapter to build a new experimental protocol to correct and analyze the impact of access resistances on current curves and parameters.Finally, the last chapter apply this new methodology to the case of stochastic mismatch between transistors. The results are then compared to the methods used by industrials and academics, each of them having their own pros and cons. The new method proposed tries to keep the best of both previous one.
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Jean-Baptiste Henry. Contribution à l'étude expérimentale des résistances d'accès dans les transistors de dimensions deca-nanométrique des technologies CMOS FD-SOI. Micro et nanotechnologies/Microélectronique. Université Grenoble Alpes, 2018. Français. ⟨NNT : 2018GREAT039⟩. ⟨tel-01897472⟩

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