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SysML Models Verification Relying on Dependency Graphs

Abstract : Formal verification of SysML models contributes to early detection of design errors early in the life cycle of systems. Incremental modeling of systems leads to the repeated verification of parts of systems models that were already verified in previous versions of the SysML model. This paper proposes to optimize the verification process by generating dependency graphs from SysML models. This revisited verification technique is now supported by TTool. It is illustrated with an Avionics Full DupleX network.
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https://hal.telecom-paris.fr/hal-03575960
Contributor : Ludovic Apvrille Connect in order to contact the contributor
Submitted on : Tuesday, February 15, 2022 - 4:44:13 PM
Last modification on : Saturday, February 26, 2022 - 3:28:58 AM
Long-term archiving on: : Monday, May 16, 2022 - 8:48:22 PM

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Ludovic Apvrille, Pierre de Saqui-Sannes, Oana Hotescu, Alessandro Tempia Calvino. SysML Models Verification Relying on Dependency Graphs. 10th International Conference on Model-Driven Engineering and Software Development, 2022, Vienna, Austria. ⟨10.5220/0010792900003119⟩. ⟨hal-03575960⟩

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