Skip to Main content Skip to Navigation
Conference papers

Reliability Analysis of a Spiking Neural Network Hardware Accelerator

Abstract : Despite the parallelism and sparsity in neural network models, their transfer into hardware unavoidably makes them susceptible to hardware-level faults. Hardware-level faults can occur either during manufacturing, such as physical defects and process-induced variations, or in the field due to environmental factors and aging. The performance under fault scenarios needs to be assessed so as to develop cost-effective fault-tolerance schemes. In this work, we assess the resilience characteristics of a hardware accelerator for Spiking Neural Networks (SNNs) designed in VHDL and implemented on an FPGA. The fault injection experiments pinpoint the parts of the design that need to be protected against faults, as well as the parts that are inherently fault-tolerant.
Complete list of metadata
Contributor : Haralampos Stratigopoulos Connect in order to contact the contributor
Submitted on : Friday, December 24, 2021 - 8:11:34 AM
Last modification on : Sunday, January 9, 2022 - 3:29:37 AM
Long-term archiving on: : Friday, March 25, 2022 - 6:08:20 PM


Files produced by the author(s)


  • HAL Id : hal-03501968, version 1


Theofilos Spyrou, Sarah A El-Sayed, Engin Afacan, Luis A Camuñas-Mesa, Bernabé Linares-Barranco, et al.. Reliability Analysis of a Spiking Neural Network Hardware Accelerator. Design, Automation and Test in Europe Conference (DATE), Mar 2022, Antwerp, Belgium. ⟨hal-03501968⟩



Record views


Files downloads