Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs - Circuits Intégrés Numériques et Analogiques Accéder directement au contenu
Communication Dans Un Congrès Année : 2022

Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs

Résumé

In this work HLS is used for designing a parametric optical flow Hierarchical algorithm in FPGAs. The algorithm that is designed is the Hierarchical (pyramid) Horn and Schunck algorithm, both a multi-rate and multi-level (multi-scale) algorithm, which achieves larger motion displacement detection than the mono-scale ones. With the help of HLS, we parametrize our design in terms of the levels of the pyramid, the iteration factor and the number of pixels computed per clock. We are reusing the same resources in each level of the pyramid to keep the usage of DSPs and RAM low. We perform a design space exploration of the algorithm and we show that our fastest design achieves a throughput of 461 Mpixel/s in a 2048×2048 resolution pixel image.
Fichier principal
Vignette du fichier
ISCAS22_OF.pdf (619.01 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)

Dates et versions

hal-03691829 , version 1 (09-06-2022)

Identifiants

  • HAL Id : hal-03691829 , version 1

Citer

Ilias Bournias, Roselyne Chotin, Lionel Lacassagne. Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs. IEEE International Symposium on Circuits and Systems (ISCAS 2022), May 2022, Austin, TX, United States. ⟨hal-03691829⟩
76 Consultations
55 Téléchargements

Partager

Gmail Facebook X LinkedIn More